dma读nand_FSMC驱动的SRAM和NAND之间可以DMA么？

应该是FSMC驱动QVGA TFT-LCD SRAM和NOR之间用DMA.

ST官方有个有关QVGA LCD驱动的文档。我看了半天没怎么明白。

2.3 Image source

The 565 format images are programmed in NOR memory.

In a first step, two images are transferred from NOR to external on-Board SRAM. External

SRAM acts as frame refresh buffer for TFT-LCD.

To implement an animated banner display, the SRAM frame buffers are updated during run

mode with new images from NOR memory. This approach is used to maintain the exact

working model of the TFT-LCD controller.

The on-board NOR memory contains the programmed images which are to be used for

display on the LCD. SRAM Double buffer management allows the source data to be updated

in run mode.

2.4 STM32 QVGA LCD-TFT direct drive flow

To achieve a static image view on a controllerless TFT, the image frame has to be refreshed

at a rate of at least 15 fps. Vertical and horizontal scanning of one frame are performed as

per the TFT-LCD module specifications.

A QVGA-LCD module single-frame display needs 320x240 pixels of data.

240 horizontal lines (each of 320 pixels) are scanned vertically on the TFT to display one

frame.

Along with data scanning, dummy data writes are required for the TFT to reach the required

horizontal and vertical front and back-porch values. These values are available the TFT

datasheet.

Dummy data writes are composed of writing zero data to the TFT RGB lines.

● DMA1_Channel1 is used for back porch data transfer

● DMA1_Channel2 is used for active data transfer

● DMA1_Channel3 is used for front porch data transfer

The FSMC is configured in asynchronous mode and operates in Mode1 which is the default

mode selected when configuring the SRAM memory type.

应该是FSMC驱动QVGA TFT-LCD SRAM和NOR之间用DMA. ST官方有个有关QVGA LCD驱动的文档。我看了半天没怎么明白。 2.3 Image source The 565 format images are programmed in NOR memory. In a first step, two images are transferred from NOR to external on-Board SRAM. External SRAM acts as frame refresh buffer for TFT-LCD. To implement an animated banner display, the SRAM frame buffers are updated during run mode with new images from NOR memory. This approach is used to maintain the exact working model of the TFT-LCD controller. The on-board NOR memory contains the programmed images which are to be used for display on the LCD. SRAM Double buffer management allows the source data to be updated in run mode. 2.4 STM32 QVGA LCD-TFT direct drive flow To achieve a static image view on a controllerless TFT, the image frame has to be refreshed at a rate of at least 15 fps. Vertical and horizontal scanning of one frame are performed as per the TFT-LCD module specifications. A QVGA-LCD module single-frame display needs 320x240 pixels of data. 240 horizontal lines (each of 320 pixels) are scanned vertically on the TFT to display one frame. Along with data scanning, dummy data writes are required for the TFT to reach the required horizontal and vertical front and back-porch values. These values are available the TFT datasheet. Dummy data writes are composed of writing zero data to the TFT RGB lines. ● DMA1_Channel1 is used for back porch data transfer ● DMA1_Channel2 is used for active data transfer ● DMA1_Channel3 is used for front porch data transfer The FSMC is configured in asynchronous mode and operates in Mode1 which is the default mode selected when configuring the SRAM memory type.