利用FFT频谱分析测量频率与幅值

之前做比赛的时候，发现这篇博客的访问量激增，意识到一丝不妙的感觉，就赶紧删除了，今天补一下。

利用FFT测频的思路是寻找最大幅值，确定最大幅值的RAM地址，再根据公式和频谱分辨率相称即可。用FFT测量幅值，我虽然没有做出来，可能是太废，但原理还是比较简单的。寻找到最大值后根据缩放因子进行左移或后移，再除于（N/2）。

module  Mre_Fre(
    input                               clk,
    input                               rst_n,
    input               [1:0]           NumKey1,
    input               [9:0]           Data_In,
    input               [9:0]           WrAddr,
    output              [19:0]      Assignment,//幅值
    output              [31:0]      Fre//频率

);


reg     [9:0]       Fre_reso;//频率分辨率
always @  (posedge clk or negedge rst_n)
    if(!rst_n)
        Fre_reso <= 1b1;
    else
        case(NumKey1)
            2d0 :
                Fre_reso <= 1b1;
            2d1 :
                Fre_reso <= 4d10;
            2d2 :
                Fre_reso <= 7d100;
            2d3 :
                Fre_reso <= 10d1000;
        endcase


//状态锁存      
reg     [9:0]       temp1,temp2,temp3;//寄存器
always @ (posedge clk or negedge rst_n)
    if(!rst_n)
        begin
            temp1 <= d0;
            temp2 <= d0;
            temp3 <= d0;
        end
    else
        begin
            temp1 <= Data_In;
            temp2 <= temp1;
            temp3 <= temp2;
        end




reg     [1:0]           status;//状态
reg     [9:0]           A;//幅值
reg     [31:0]      F;//频率
reg                     Flag;//峰值标志位

always @ (posedge clk or negedge rst_n)
    if(!rst_n)
        begin
            status <= d0;
            A <= d0;
            F <= d0;
            Flag <= d0;
        end
    else
        case(status)
            2d0 :
                if(WrAddr == 10d1)
                    begin
                        status <= 1d1;
                        A <= d0;
                        F <= d0;
                        Flag <= d0;
                    end
                else
                    begin
                        Flag <= d0;
                        status <= d0;
                    end
            2d1 :
                if(WrAddr <= 10d512)
                    begin
                        status <= 1d1;
                        if(temp2 - temp1 > 3d5 && temp2 > temp3)
                            begin
                                if(temp2 >= A)
                                    begin
                                        F <= WrAddr - 2;//Ram的特性，会有两个地址的延迟。
                                        A <= temp2;
                                    end
                            end
                    end
                else
                    begin
                        Flag <= 1b1;
                        status <= d2;                      
                    end
            2d2 :
                status <= d0;

        endcase

assign  Fre = Flag ? F*Fre_reso : Fre;
assign  Assignment = Flag ? A * 2 : Assignment;

/*
always @ (posedge clk or negedge rst_n)
    if(!rst_`
````

        Fre <= d0;
    else if(status == 3d2)
        Fre <= F*Fre_reso;
    else
        Fre <= Fre;
*/



endmodule